| The P80C557E4/P83C557E4/P89C557E4
(hereafter generically referred to as P8xC557E4) single-chip
8-bit microcontroller is |
| manufactured in an advanced
CMOS process and is a derivative of the 80C51 microcontroller
family. The P8xC557E4 has the same |
| instruction set as the 80C51.
Three versions of the |
| derivative exist: |
| *
P83C557E4 - 32 Kbytes mask
programmable ROM |
| *
P80C557E4 - ROMless version
of the P83C557E4 |
| *
P89C557E4 - 32 Kbytes FEEPROM (Flash-EEPROM)
|
| The P8xC557E4 contains a non-volatile
32 Kbytes mask programmable ROM (P83C557E4) or electrically
erasable FEEPROM |
| respectively (P89C557E4),
a volatile 1024 � 8 read/write data memory, five 8-bit
I/O ports , one 8-bit input port, two 16-bit timer/event
|
| counters (identical to the
timers of the 80C51),an additional 16-bit timer coupled
to capture and compare latches, a 15-source, two- |
| priority-level,nested interrupt
structure, an 8-input ADC, a dual DAC pulse width modulated
interface, two serial interfaces |
| (UART and I2C-bus), a "watchdog"
timer, an on-chip oscillator and timing circuits. For
systems that require extra capability the P8xC557E4
|
| can be expanded using standard
TTL compatible memories and logic. In addition, the
P8xC557E4 has two software selectable modes of |
| power reduction - Idle Mode
and power-down mode. The Idle Mode freezes the CPU while
allowing the RAM, timers, serial ports, and |
| interrupt system to continue
functioning. The power-down mode saves the RAM contents
but freezes the oscillator, causing all other chip |
| functions to be inoperative.
The device also functions as an arithmetic processor
having facilities for both binary and BCD arithmetic |
| as well as bit-handling capabilities.
The instruction set consists of over 100 instructions:
49 one-byte, 45 two-byte, and 17 three-
byte. With |
| a 16 MHz
system clock, 58% of the instructions are executed in
0.75μs and 40% in 1.5μs. Multiply and divide instructions
require 3μs. |
| P8xC557Ex factsheet |
